SRAM-and-DRAM

The difference between SRAM and DRAM, what is SRAM & DRAM?

We are going to learn about the two of the most common types of random access memories which are quite commonly used inside the computers. That is SRAM and DRAM. Thus, this SRAM represents the Static RAM, while this DRAM represents the Dynamic RAM.

(The reason it is known as the dynamic RAM because in case of this memory we need to perform the periodic refresh cycles. So, now let's see the difference between this SRAM and DRAM in terms of the different aspects.anyway, let us see the differences between this SRAM and DRAM in terms of the different aspects.  So, this SRAM is used as cache memory inside the computer, while this DRAM is used as a main memory inside the computer. )

And the reason this SRAM is used as cache memory is, because of its speed. Because this SRAM is the fastest among all the memories. While if you see the speed of this DRAM, this DRAM is faster compared to the primary storage element like hard disk drive, but it is slower compared to this SRAM. So, although the speed of this SRAM is quitefast, if you see in terms of the cost then in terms of the cost this SRAM is costliest among all the memories. 

While on the off chance that you see the DRAM, it is less expensive contrasted with this SRAM. And if you see the density of this SRAM and DRAM, that is the number of memory cell per unit area, then in that case also the SRAM has lower density compared to the DRAM. So, apart from this aspects, another as pectin which we can compare this two RAMs is the power consumption. 

So, if you see the power consumption of this SRAM, it is lesser compared to the DRAM. But when we operate this SRAM at higher frequencies,then the power consumption of this SRAM and DRAM are comparable. So, these are the basic differences between the SRAM and the DRAM. Now, let's understand why these differences are present between this SRAM and DRAM. That means why the speed of this SRAM is fast compared to the DRAM or let's say why the density of this SRAM is lower compared to the DRAM. So, to understand that we need to see how this SRAM and DRAM works. 

And to see that we need to understand the internal structure of this SRAM as well as the DRAM. So, first of all, let us see the internal structure of this DRAM. So, if you see the one bit of the DRAM cell,then it consists of one transistor and one capacitor. Along these lines, in the event of the DRAM cell, the memory bits are put away as charge over this capacitor. So, by charging and discharging the capacitor,we can know that whether the bit that is stored inside this capacitor is logic 1 or logic 0. 

So, now in case of this DRAM cell, we can access this capacitor by using this pass transistor. So, when this pass transistor is turned ON,then we can read the capacitor data or we can write onto this capacitor. And when this pass transistor is OFF, then the charge across the capacitor should remain as it is. So, in the ideal case, this capacitor should not lose its charge. 

But in the actual case, if you see, there will be some leakage current and because of that, the capacitor will lose its charge gradually. And that is the reason, this dynamic cell requires the periodic refresh cycles. And that is the reason behind it, why this memory is known as the Dynamic RAM. So, now as we know about the internal structure of this dynamic RAM, let us see, how to read and write operations are being performed on this dynamic RAM. So, like I said to read the data of this DRAM,first of all, we need to turn on this pass transistor. And that can be done by applying the voltage to this word line. So, once the voltage is being applied to this word line, then the charge across this capacitor will be available at this bit line. So, just by using the sense amplifier, we can read the voltage that is available at this bit line. So, now if you observe this read cycle, in this read cycle once this pass transistor is ON, then the data or the charge across this capacitor will be available at the bit line. So, eventually, this capacitor will lose its charge during the read operation. 

So, such kind of read operations is known as the destructive read operation. And to avoid that we need to perform the refresh operation after every read cycle so that the capacitor can get its original charge. So, now to increase the read operation speed this bit line is charged with the finite voltage. Now, let us understand, why this recharge very important. So, let's say, initially, the voltage across the capacitor is 2V. And the 2V represents the logic 1. And the 0V represents the logic 0. So, once the read operation starts, this pass transistor will be turned ON. and the voltage across this capacitor gradually will be available at the bit line. So, the bit line will start charging from the 0V to the 2V. Ans once it will reach from 0 to 2V, then this sense amplifier will get to know that the voltage across the capacitor is 2V or logic 1. 

But instead of that suppose if we have recharged this bit line to the 1V, then the time that is required to reach from 1V to the 2V will be almost half. So, in this way, by pre-charging this bit line by some finite value, we can reduce the read time or we can increase the read speed. And further we can increase this reading speed,just by sensing the trend in which this bit line voltage is going. So, instead of waiting for this bit line to reach from 1V to the 2V, suppose if we just measure the incremental voltage across this bit line and if we amplify it after the sense amplifier, then the time of this read operation will further reduce. So, in this way, by using this method, we can reduce the read time of this dynamic RAM. 

So, similarly now let's see how the write operation is being performed. So, during the write operations, all the bit lines are being recharged with some finite value. And for the particular bit line on which we want to write, the bit voltage is applied to that particular bit line. So, let's say, we want to charge this capacitor then the bit voltage will be applied to this particular bit line. And then after this pass transistor is turned ON. So, whatever voltage that is available at this bit line, will be transferred to this capacitor. And in this way, we can write on this DRAM. 

So, this is how the read and write operations are being performed on this DRAM. So, now as this DRAM involves the capacitors,so the reading and writing speed of this DRAM depends upon the charging and discharging time of this capacitors. Similarly, let us see the internal structure of this SRAM and let us see how reading and writing is performed on this SRAM. So, if you see the internal structure of thisSRAM, it consists of 6 transistors. So, out of the 6 transistors, the two transistors are the pass transistors which will give access to the bit lines, while the reaming four transistors are the two cross-coupled inverters. So, here this transistor 1 and 2, is the first CMOS inverter pair and the transistor 3 and 4 are the second CMOS inverter pair. 

So, if you see the simplified circuit, then the simplified circuit will look like this. So, in case of this SRAM cell, the memory bit is stored between this two cross-coupled inverters. So, let us say if we have latched logical 1 then at the output of the first inverter we will have logic 0. And again at the output of the second inverter,we will have logic 1. So, as far as the power is supplied to this SRAM, the logic 1 will be get circulated between these two inverter pairs. So, unlike in case of the dynamic RAM cell,we do not require any kind of refresh cycles during this SRAM operation. And that is the reason, this SRAM is known as the static RAM. So, apart from this 6 transistor design ofthis SRAM cell, we also have 4 transistor design. So, in case of this 4 transistor design, the p-MOS are replaced by the high impedance resistors. 

So, in this way by using the 4 transistor design, we can reduce the number of bits that are required for the 1 bit of storage. But the disadvantage of this 4 transistor design is that the continuous power will be get dissipated across this resistors. So, whenever we require the less power consumption,then the 6TH design is more preferred over this 4 transistor design. So, as you can see in case of this SRAM cell,the number of transistors that is required is 6 times more compared to the DRAM. And that is the reason, the density in case of the DRAM is more than the SRAM cell. And that is the reason why this SRAM is costlier compared to the DRAM. Because the cost per bit in case of the SRAM will increase compared to the DRAM. 

So, that is being said, now let us understand how to read and write operations are being performed on this SRAM. Now, to perform the read operation, first of all, these two pass transistors, are turned ON by applying the voltage to this word line. So, once these pass  transistors are turned ON, then whatever voltage that is available at this point, let's say Q, that will be available at the bit line. And whatever voltage that is available att his point, let's say Q bar, that will be available at the bit line bar. So, suppose at this point let us say we have logical 1, then at bit line, we will get logical 1. And at this point, we will get logical 0. And using the sense amplifier, we can sense this voltage and we can read that voltage of this SRAM cell. Now, you might ask that this can be performed only by the single bit line, so what is the need of having two bit-lines. So, two bit lines are required to increase the speed of this read and write operations. 

So, let's understand how this two bit lines,will enhance the speed of this read and write operations. So, here in case of the SRAM also, these bit lines are pre-charged with some finite value. So, let's say if this SRAM has two volts as logical 1, and 0 volts as logical 0, then generally this bit lines are recharged with the voltage of 1 V. Now, let's also assume that the voltage that is being read through this SRAM is logical 1. So, at this point, we will have 2 V of voltage and this point we will have 0 V of voltage. So, as soon as this pass transistor is turned ON, the voltage at the bit line will be equal to 2 V. But this transition from 1 V to 2V will take some time. Similarly, at this bit line bar, we will have voltage from 1 V to the 0 V. And this transition will also take some time. So, instead of waiting for the voltage to reach from 1 V to 2V, and from 1 V to 0V, if we simply see the trend in which h the voltage is going then we can increase the speed of this read cycle. 

So, as you can see here, we are taking the difference between the bit line and the bit line bar voltages. So, here if the voltage is increased from 1 V to the 1.1 V, and let's say here the voltage is reduced from 1V to the 0.9 V then if just differentiate this two voltages and amplify it then we can easily sense that voltage. And in this way, we can increase the read speed or reduce the read time. Similarly, let us see how write operation is being performed. So, during the write operation, whatever voltage we want to write on this inverter pair, we need to apply that voltage to this bit lines. So, let's say we are applying logical 1 to this bit line. And the initial voltage or initial bit that is being stored inside this inverter pair is logical 0. So, at the bit line bar we will apply the logical 0. So, now whenever we turned ON this pass transistor,the bit line voltage will be applied to this inverter. And this inverter will try to reduce the voltage of this bit line to the logical 0. But at the same time, if you see over here,this logical 0 will be applied to input of this inverter. 

So, that will drive the output of this inverter to the logic 1. And that logic 1 will drive the output of the first inverter to the logic 0. So, in this way, the value of logical 1 will be latched inside this inverter. So, in this way, by having the two bit lines,we can drive the bit line voltages into this inverter pair very easily. So, by having two bit lines, we can increase the speed of read and write operations. So, so far as we have seen in case of the SRAM cell, it does not involve any kind of capacitors. So, the transition from 1 to 0 will be faster in case of SRAM in compared to the DRAM, where it involves the charging and discharging of the capacitors. And that is the reason, this SRAM is quite faster compared to the DRAM. So, as we have seen so far, this SRAM consists of 6 transistors, while the DRAM consists of only 1 transistor. And that is the reason this SRAM is quite costly compared to the DRAM, as well as the density of this SRAM is low compared to the DRAM. And as this DRAM involves the capacitor charging and discharging, as well as the refresh cycles, so the speed of this DRAM is less compared to the SRAM. So, this is all about the differences between the SRAM and DRAM.

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